Intel cancels next-generation Xeon for even-more-next-generationXeon
Tigerton, get used to that name. Apparently it's gonna have
Hypertransport in it. :-) Intel Shifts Plans for Server Chips: Financial News - Yahoo! Finance http://biz.yahoo.com/ap/051024/intel...hips.html?.v=2 PS- oh, and it's also delaying the Montecito Itanium, as EdG posted. Yousuf Khan |
Intel cancels next-generation Xeon for even-more-next-generation Xeon
On Mon, 24 Oct 2005 21:06:39 -0500, EdG wrote:
On Mon, 24 Oct 2005 20:01:21 -0400, Yousuf Khan wrote: Tigerton, get used to that name. Apparently it's gonna have Hypertransport in it. :-) Intel Shifts Plans for Server Chips: Financial News - Yahoo! Finance http://biz.yahoo.com/ap/051024/intel...hips.html?.v=2 PS- oh, and it's also delaying the Montecito Itanium, as EdG posted. Yousuf Khan Wasn't Intel talking about using a high-speed interconnect a long time ago, maybe a year or two before Opteron? GIO or something? What happened with that? Well there was NGIO and then 3GIO, which became PCI Express. IIRC 2007 is the scheduled intro of the common Intanium/x86 bus, which is expected to be an integrated memory controller architecture a packetized I/O bus -- CSI or sumthin'??. And not long ago I read somewhere Intel was going to use a dual bus like the one AMD used on the Athlon MP, I can only hope that was false or they have now dumped that too, I doubt it would get them far, still a shared bus right? I believe the dual independent bus is scheduled for next year some time with the new 65nm & P-M derived desktop/server chips... dunno if that's what Bensley is supposed to be. All those damned code names drive me nuts. -- Rgds, George Macdonald |
Intel cancels next-generation Xeon for even-more-next-generation Xeon
EdG wrote:
Wasn't Intel talking about using a high-speed interconnect a long time ago, maybe a year or two before Opteron? GIO or something? What happened with that? Yeah, that was 3GIO, which became Arapahoe, which became PCI-Express. That was in a futile attempt to derail any momentum building for AMD's Hypertransport. Of course PCI-E is no competition for HT, it's much too bloated to be a chip-to-chip interconnect. AMD never fell for it, and kept HT as simple as possible while Intel threw as much bling-bling into PCI-e to dazzle people with features. Now it looks like AMD might even use PCI-e against Intel, if the rumours about AMD building a PCI-e link directly into its processors can be believed. And not long ago I read somewhere Intel was going to use a dual bus like the one AMD used on the Athlon MP, I can only hope that was false or they have now dumped that too, I doubt it would get them far, still a shared bus right? Yeah, I think that was supposed to be in the Deerfield processor that Intel just cancelled. Yousuf Khan |
Intel cancels next-generation Xeon for even-more-next-generation Xeon
On 25 Oct 2005 12:00:45 -0700, "YKhan" wrote:
EdG wrote: Wasn't Intel talking about using a high-speed interconnect a long time ago, maybe a year or two before Opteron? GIO or something? What happened with that? Yeah, that was 3GIO, which became Arapahoe, which became PCI-Express. That was in a futile attempt to derail any momentum building for AMD's Hypertransport. Of course PCI-E is no competition for HT, it's much too bloated to be a chip-to-chip interconnect. AMD never fell for it, and kept HT as simple as possible while Intel threw as much bling-bling into PCI-e to dazzle people with features. Now it looks like AMD might even use PCI-e against Intel, if the rumours about AMD building a PCI-e link directly into its processors can be believed. And not long ago I read somewhere Intel was going to use a dual bus like the one AMD used on the Athlon MP, I can only hope that was false or they have now dumped that too, I doubt it would get them far, still a shared bus right? Yeah, I think that was supposed to be in the Deerfield processor that Intel just cancelled. Yousuf Khan The whole fleet of next years Xeons (now heating up verification labs at select OEMs) use a separate hose for each processor to MCH connection. They're not going to get to 1333mhz fsb speeds with daisy-chains... |
Intel cancels next-generation Xeon for even-more-next-generation Xeon
On Tue, 25 Oct 2005 17:37:08 -0400, daytripper wrote:
On 25 Oct 2005 12:00:45 -0700, "YKhan" wrote: EdG wrote: Wasn't Intel talking about using a high-speed interconnect a long time ago, maybe a year or two before Opteron? GIO or something? What happened with that? Yeah, that was 3GIO, which became Arapahoe, which became PCI-Express. That was in a futile attempt to derail any momentum building for AMD's Hypertransport. Of course PCI-E is no competition for HT, it's much too bloated to be a chip-to-chip interconnect. AMD never fell for it, and kept HT as simple as possible while Intel threw as much bling-bling into PCI-e to dazzle people with features. Now it looks like AMD might even use PCI-e against Intel, if the rumours about AMD building a PCI-e link directly into its processors can be believed. And not long ago I read somewhere Intel was going to use a dual bus like the one AMD used on the Athlon MP, I can only hope that was false or they have now dumped that too, I doubt it would get them far, still a shared bus right? Yeah, I think that was supposed to be in the Deerfield processor that Intel just cancelled. Yousuf Khan The whole fleet of next years Xeons (now heating up verification labs at select OEMs) use a separate hose for each processor to MCH connection. They're not going to get to 1333mhz fsb speeds with daisy-chains... Ok, but am I the only one who detects Intel trying to defend the indefensable? IBM tried to hold the "upper ground" too, oh, about 15 years ago. ...and had a better position (different ISA). -- Keith |
IBM defends the indefensible
keith wrote:
Ok, but am I the only one who detects Intel trying to defend the indefensable? IBM tried to hold the "upper ground" too, oh, about 15 years ago. ...and had a better position (different ISA). Hey, speaking of IBM defending the indefensible. They just picked up Solaris as one of their OS choices on their blade servers. Sun freezes hell, gets IBM to sell Solaris on blades | The Register http://www.theregister.co.uk/2005/10..._solarisblade/ Yousuf Khan |
IBM defends the indefensible
On Thu, 27 Oct 2005 20:54:34 -0400, Yousuf Khan wrote:
keith wrote: Ok, but am I the only one who detects Intel trying to defend the indefensable? IBM tried to hold the "upper ground" too, oh, about 15 years ago. ...and had a better position (different ISA). Hey, speaking of IBM defending the indefensible. They just picked up Solaris as one of their OS choices on their blade servers. Sun freezes hell, gets IBM to sell Solaris on blades | The Register http://www.theregister.co.uk/2005/10..._solarisblade/ No $#|+! Global warming? Hell *has* frozen! ;-) -- Keith |
IBM defends the indefensible
"Yousuf Khan" wrote in message ... keith wrote: Ok, but am I the only one who detects Intel trying to defend the indefensable? IBM tried to hold the "upper ground" too, oh, about 15 years ago. ...and had a better position (different ISA). Hey, speaking of IBM defending the indefensible. They just picked up Solaris as one of their OS choices on their blade servers. Sun freezes hell, gets IBM to sell Solaris on blades | The Register http://www.theregister.co.uk/2005/10..._solarisblade/ Yousuf Khan You must have missed this back in june.... http://news.com.com/IBM+backs+Suns+S...3-5764485.html remember the new ibm motto, "anything for a buck" :-) del |
Intel cancels next-generation Xeon for even-more-next-generation Xeon
Yeah, that was 3GIO, which became Arapahoe, which became PCI-Express.
That was in a futile attempt to derail any momentum building for AMD's Hypertransport. Of course PCI-E is no competition for HT, it's much too bloated to be a chip-to-chip interconnect. AMD never fell for it, and kept HT as simple as possible while Intel threw as much bling-bling into PCI-e to dazzle people with features. How is it bloated, oh font of interconnect wisdom? Perhaps you don't realize it, but serial interconnects are far higher bandwidth... Now it looks like AMD might even use PCI-e against Intel, if the rumours about AMD building a PCI-e link directly into its processors can be believed. I don't see how that is "using PCI-e against Intel"... And not long ago I read somewhere Intel was going to use a dual bus like the one AMD used on the Athlon MP, I can only hope that was false or they have now dumped that too, I doubt it would get them far, still a shared bus right? Yeah, I think that was supposed to be in the Deerfield processor that Intel just cancelled. No it's not cancelled moron. Deerfield is a LV IPF part. They cancelled Whitefield. White, not deer. Intel's next gen server chipset is a wonderful piece of work and features dual independent FSBs. I suspect the next generation after that will feature 4 or more. David |
IBM defends the indefensible
"Del" == Del Cecchi writes:
Del "Yousuf Khan" wrote in message Del ... keith wrote: Ok, but am I the only one who detects Intel trying to defend the indefensable? IBM tried to hold the "upper ground" too, oh, about 15 years ago. ...and had a better position (different ISA). Hey, speaking of IBM defending the indefensible. They just picked up Solaris as one of their OS choices on their blade servers. Sun freezes hell, gets IBM to sell Solaris on blades | The Register http://www.theregister.co.uk/2005/10..._solarisblade/ Yousuf Khan Del You must have missed this back in june.... Del http://news.com.com/IBM+backs+Suns+S...3-5764485.html Del remember the new ibm motto, "anything for a buck" :-) Del del Actually no surprise here. This is the direction IBM has been moving for some time and that is OS neutral. IBM has been changing to a service company and has stated that clearly. The only hardware division IBM wants to keep is the mainframe division because there is very little competition and it is still a cash cow. Heck if they can sale windows they can sale anything ;-)). Well depends on the contract with M$, but I think after the last anti-trust lawsuit that M$ won't have a contract like that soon. Whatever. Alan |
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